Probe card assembly systems are used in integrated circuit (IC) manufacturing to translate electrical signal paths from the tightly spaced electrical interconnection pads on ICs to the coarsely spaced electrical interconnection pads on printed circuit boards that interface to IC test systems.
Advances in semiconductor integrated circuit wafer design, processing, and packaging technologies have resulted in increases in the number of input/output (I/O) pads on each die and as well as in an increase in the diameter of the silicon wafers used in device fabrication. With more die to test per wafer and each die having more I/O pads, the cost of testing each die is becoming a greater and greater fraction of the total device cost. This undesirable trend can only be reversed if either the test time required for each die is reduced or else multiple die are tested simultaneously. If multiple die are tested simultaneously, then the requirements for parallelism between the probe tips and the semiconductor wafer and the co-planarity of the probe tips become increasingly stringent since all of the probe tips are required to make good electronic contact at the same time over a large area on the wafer.
In the prior art, probe card assembly systems have been equipped with various types of mechanical mechanisms designed to affect in-situ parallelism adjustment of the probe tips relative to the semiconductor wafer to insure that adequate electrical contact is made to all of the probed devices on the wafer.
Evans et al (U.S. Pat. No. 4,975,638) teach a method of correcting parallelism errors between the probe tips on a membrane probe card and a semiconductor wafer under test. Evans et al teach a test probe card which includes a flexible, thin film contactor which is subjected to pressure by a rigid pressure block having two degrees of freedom that permit the block to orient itself parallel to the plane of the IC device being tested and impose an evenly controlled force on the probe contacts carried by the contactor. Evans et al claims that the significant advantage of their invention is that the probe contacts carried by the flexible film contactor of the test probe card all lie in a common plane and are maintained in this plane in the course of a testing procedure.
In probe card assembly systems according to Eldridge et al (e.g. U.S. Pat. No. 6,624,648 and U.S. Pat. No. 5,974,662, parallelism errors between their probe tips and the semiconductor wafer are corrected by adjusting the orientation of a space transformer using multiple ball tipped linear actuators. The space transformer also serves as the support substrate for composite probe elements fabricated as described in the patent specification, each of which are individually mounted on the space transformer. Eldridge et al state that an object of their invention is that the space transformer, and hence, the tips of their elongate resilient probe elements can be “oriented without changing the position of the probe card”.
The examples of Evans and Eldridge given above are presented as exemplary methods for correcting parallelism errors between the plane of the probe tips and the reference surface of the probe card on which they are mounted. It is well known to those knowledgeable in the field that semiconductor wafer probers provide a head plate with a probe card mounting surface that is precisely aligned (mechanically) to be parallel to the plane in which the surface of the wafer chuck travels, that is the wafer reference surface (WRS). Thus if the parallelism error between the tips of a probe card relative to the probe card mounting surface are within acceptable tolerances, then the probe card can be mounted on a wafer prober head plate with high confidence that the probe tips will be parallel to the plane of travel of the wafer chuck, i.e. the WRS, and therefore to the surface of semiconductor wafer under test.
During the process of electrical testing of the integrated circuits (die) on a semiconductor wafer in a semiconductor wafer prober, the wafer chuck translates the surface of the wafer under test through a plane that is parallel to the WRS. As mentioned previously, the WRS is pre-adjusted to be parallel to the plane of the probe card interface assembly mounting surface in the wafer prober head plate. The semiconductor wafer under test is reversibly yet precisely mounted on the WRS of the wafer chuck, such as by electrostatic means or by an applied vacuum, thereby requiring the wafer to mechanically conform to the WRS. The surface of the semiconductor wafer is thus affixed and positioned so as to be precisely in a plane that is parallel to the WRS of the wafer chuck.
To test more than one die on a semiconductor wafer, simultaneous low-resistance electrical contacts must be established with positionally matching sets of spring probes, such as but not limited to stress metal spring (SMS) probe tips, for each die to be tested. The more die to be tested simultaneously, the greater the degree of parallelism that is required between the spring probes and the surface of the semiconductor wafer, i.e. the WRS, in order to insure that the probe tip scrub, and hence electrical contact, is uniform across the wafer. However, as higher numbers of die are tested in parallel, the number of simultaneous interconnects from the IC to the probe card assembly to the IC tester increases (not assuming pin multiplexing). Since probe tips for contacting the bonding pads on IC wafers require sufficient mechanical force on a per connection basis to assure a reliable low resistance connection, the total force between the probe card assembly and the wafer increases in proportion to the number of connections. The force between the IC tester and the probe card assembly also increases on a pin by pin basis when pogo pins are used as the electrical interface, however, there is a growing trend toward the use of zero insertion force connectors (ZIF) to reduce the force between the probe card and the IC tester.
A Precision Point VX probe card measurement tool, available through Applied Precision, LLC, of Issaquah, WA, is capable of measuring parallelism error between the probe tips and the mounting surface of a probe card by measuring the relative “Z height” of each individual probe tip on the probe card through a measurement of the electrical conductivity between the probe tips and a highly polished electrically conductive tungsten surface of a so called checkplate. In order to obtain planarity measurements with the Precision Point VX that are accurate to within the manufacturers specification of 0.1 mils (2.5 microns) across the full X and Y dimensions of the checkplate, the parallelism between the checkplate and the “Support Plate” which holds the probe card “Mother Board” must be mechanically adjusted following a procedure specified by the manufacturer and referred to as the “Fine Leveling calibration procedure.” Because the reference surface on the “Mother Board” may be different for the Precision Point VX and a wafer prober, it is necessary to perform the fine leveling procedure or else significant errors may be introduced into the planarity measurement.
If all of the probe tips are co-planar, then any parallelism error of the probe tips relative to the mounting surface of the probe card can be measured, such as by using the Precision Point VX. The amount of parallelism correction required can be estimated from the data detailing the height of the first to the last probe tip to touch the checkplate. The parallelism error can them be corrected and the results verified on the Precision Point VX.
There are, however, several limitations to this method of parallelism correction and verification using Precision Point VX. First, it is time consuming. Verification can take four hours or more. Second, if the measurement is made under simulated tester interface force loading conditions, it may not include all aspects of the mechanical deflection associated with the forces applied during actual operation in a wafer prober. Third, the measurement may be done at room temperature and may not be indicative of the actual operating temperature which will induce mechanical changes due to the thermal coefficients of the various materials in the probe card assembly.
It is also possible to adjust the parallelism of the probe tips on the wafer prober. However, this is problematic because wafer probers are generally used in production environments and such activities may not be desirable. Additionally, special equipment or tooling may be required that can cause additional complication and chance for error. In any case, it is an additional burden on the user if it is required to adjust the planarity of the probe tips each time the probe card is moved from one wafer prober to another or from a quality control (QC) test instrument, such as from the Precision Point VX to a wafer prober.
There is a need for a probe card assembly system in which the parallelism of the probe tips relative to the semiconductor wafer is pre-set at the factory and no in-situ adjustment is necessary, even after changing the probe tip assembly. With such a system, it would be possible to change the probe tip assembly for cleaning, repair, or replacement or to accommodate work flow changes without the need to re-adjust the parallelism of the probe tips. With a probe card assembly having a pre-set parallelism adjustment, the customer could then keep on hand an adequate inventory of spare probe tip assemblies and would need to purchase only as many probe card assemblies as was necessary to sustain their peak throughput requirement.
It would be advantageous to provide a probe card assembly system that resists deflection under the forces generated when the probe tips are compressed during testing, i.e. due to upward displacement of the wafer prober chuck beyond the point at which the probe tips touch the wafer surface. Such a probe card assembly system would constitute a major technical advance.
Furthermore, it would be advantageous to provide a probe card assembly system that maintains low resistance electrical connections to a device under test at either elevated or depressed operating temperatures. Such a probe card assembly system would constitute a further technical advance.
As well, it would be advantageous to provide a probe card assembly system that comprises components with mechanical surfaces that are sufficiently flat and parallel to one another, to enable them to act as reference surfaces for other components either within the probe card assembly system, or that interface to the probe card assembly system. Such a probe card assembly system would constitute a further major technical advance.
It would be further advantageous to provide such a probe card assembly system having relatively flat and parallel component surfaces, that more evenly distribute and vertically transmit the high forces associated with high I/O count ICs and testers, to reduce peak-to peak mechanical deflections within the probe card assembly system, wherein the forces are generated either by the various spring pre-loading mechanisms or by the compression of the spring probes during wafer testing. Such a probe card assembly system would constitute a further major technical advance.
There is also a need for probe card assembly systems having components with improved flatness and parallelism that can rest against each other since such surfaces can enable pre-aligned, easy to replace components and sub-assemblies. Relatively flat and parallel surfaces and probe tip arrays having smaller deviations from co-planarity reduce the need for planarity adjustment. Additionally, relatively flat and parallel reference surfaces can also enable the use of very low force interposers, e.g. 0.05 g to 5 g per contact, to make low resistance high-density electrical connections over large areas, e.g. 1,000 sq cm for 300 mm wafers. Furthermore, low force interposers combined with flat and parallel reference and support surfaces enable simpler methods of clamping and achieving and maintaining planarity. Alternatively, large area components such as mother boards, Z-blocks, etc. with flat surfaces enable the use of vacuum actuated systems to achieve high levels of surface parallelism. Additionally, large area solid electrical interface connections fabricated with materials such as solder, gold wire bond bumps, plated bumps, or adhesives all have higher manufacturing yields and perform better and more reliably with flatter and more parallel interconnection support surfaces.
As well, time is often critical factor for users of probe card assemblies, such as semiconductor manufacturers and testers. However, conventional probe card assemblies typically comprise one or more key components that have long lead times, such as for multilayered ceramic components. As conventional assembly structures and manufacturing methods include such long lead time components, that the resulting fabrication cycle for one or more assemblies is long.
It would therefore be further advantageous to provide probe card assembly structures and methods having improved, i.e. rapid, fabrication cycles, for which portions of the probe card assembly can be fabricated, assembled, and/or pre-planarized, while long-lead lead time components, such as complex, custom, or semi-custom components, are readily mountable and/or remountable from the other components and assemblies. Such a probe card assembly system would constitute a further major technical advance.